Introduction to nano-scale protective thin films and their applications in semiconductor manufacturing, interdisciplinary and multidisciplinary aspect and technological quality
Conventional demands for development in semiconductor industry are changing as the Moore’s Law (stating that transistor density on integrated circuits doubles about every two years) approaching to its limits. Continuous decrease in the size of the transistors is coming close to atomic levels creating a fundamental barrier for further process developments as the semiconductor manufacturing is established today (M. Dubash, Techworld.com, April 2005). Development needs are not solely based on device scaling anymore. Rapid introduction and conceptualization of new automotive, medical and implantable devices challenge the needs to improve device performance in addition to cost reduction zero defectivity and enhanced reliability (J. Ruzyllo, Interface, V.15, No.4, 2006). Although mainstream semiconductor engineering could involve tradeoffs between performance and reliability, the new applications face assessing the impact of new materials, dealing with limited margins, advances in processing, materials science, chemistry, and more rigorous customer expectations (C.Henderson, Semitracs Inc., 2008). Introduction of copper as an interconnect material, the growing number of interconnect levels, use of low-k dielectrics as inter-metal insulators, high-k materials for ferroelectric memory applications, broad acceptance of chemical mechanical planarization (CMP) in mainstream silicon manufacturing and new packaging requirements exemplify this trend.
In CMOS manufacturing fundamental device scaling challenges have mainly arose at 50-100nm feature size requiring advanced materials for gate dielectrics and contacts (Handbook of Semiconductor Manufacturing, R. Doering, Y. Nishi, CRC Press, 2008). Furthermore, new ideas on reduced power consumption and energy harvesting introduced ferroelectric and magnetic memories, as well as piezoelectric transducers which involve materials hard to integrate to conventional semiconductor manufacturing. All these materials need to be integrated within the circuits by accounting for the compatibility with the surrounding layers to assure good adhesion and minimize delamination. Therefore, it became critical to evaluate the stresses that will form at the interfaces when new materials are used. Stresses created by thin film deposition can be classified into three types including epitaxial, thermal and intrinsic stresses (M.F. Dorner, W.D. Nix, Critical Reviews in Solid State and Material Science 14, CRC Press, 1988). Lattice matching between a thin film and substrate is defined as the epitaxial stress which is studied extensively in semiconductor manufacturing for epitaxy. Thin films are exposed to thermal stresses when the thermal expansion coefficient of the film is different than the substrate. It can arise due to elevated film deposition or the temperature changes during the progression of the processes. Intrinsic stress refers to the stress resulting from process that will cause a thin film to change its density such as the grain boundary growth in a polycrystalline film which results in denser films due to the removal of less dense grain boundaries as compared to the interior of the grain. A very nice review of the boundaries and formulations of the stresses created in thin films has been presented by Cammarata, who continues his research on thin films at the Department of Materials Science and Engineering of Johns Hopkins University (R.C. Cammarata, Journal of Electronic Materials, V. 26, No. 9, 1997). A critical thickness is defined for the thin films above which it is thermodynamically favorable for the film to partially or fully relax through misfit dislocations. Therefore, stress distribution within the thin films has been extensively studied for applications such as corrosion prevention, coatings and microelectronics. New techniques have been introduced such as evaluation of residual stress driven delamination between a copper film superseded with a nono-scale film on a silica substrate (A. Bagchi et al. Journal of Materials Research, V. 9, No. 7, 1994). Stresses and delamination properties have also been studied in uniaxial tension experiments for nonometer size metallic films on a polymeric substrate (B.E. Alaca et. al, Acta Materialia, V. 50, 2002).
Although choosing compatible materials for thin film deposition is the first approach, there are new techniques to relieve the strain in a strained layer through implanting elements into at least one of the regions of the thin film. Element implantation has to be sufficient to measurably modify the strained state of the film after a thermal anneal (Y-M. Le Vaillant, US Patent # 7473620, S.O.I Tec, Bernin, FR, 2009). Another approach to control interfacial stresses between two materials is to utilize an intermediate layer that will help adhesion to the new layer. One example of this is the use of self protective oxide films for the bonding pads during packaging of circuits. It has been demonstrated that self protective oxide film of aluminum on the aluminum contact pads highly reduced corrosion due to moisture led through the plastic material which is used to encapsulate the chip during packaging (Y.S. Kim, US patent # 5595934, Samsung Electronics Co., Suwon, KR, 1997). Self protective oxide films comply with the epitaxial stress requirements as the lattice constants match to the substrate (native metal of the oxidized film) and they are self limiting in growth as the formation of the oxide stops the ongoing chemical reaction before a critical thickness is reached. They are continuous, pore free, adherent, non-volatile and non reactive. Therefore, they are capable of preventing corrosion (such as formation of self protective aluminum oxide on aluminum). Self protective oxide films are also critical for the nuclear power plant safety. Austenitic stainless steel is used in reactor vessels at high temperatures due to its resistance to corrosion. However, this material is subject to stress corrosion cracking due to mechanical and environmental factors. Dissolution of metallic atoms into the surrounding water and the formation of an oxide film are important factors to be considered to understand crack propagation mechanism (N.K. Das et al., Corrosion Science, V. 51, 2009). Self protective oxide films are also utilized in semiconductor manufacturing for some of the processes such as chemical mechanical planarization (CMP). CMP process employs slurries that involve an aggressive chemistry to alter the properties of the film to be polished and this film is removed by the mechanical actions of the particulates in the suspension. In an optimal CMP slurry design for metal layers, the formation of the metal oxide film should be self-limiting and once formed, it must protect the underlying metal from the further attack of the slurry chemicals. This is necessary to polish the higher level metal while protecting the lower levels, in other words, to achieve topographic selectivity and hence provide planarization (F.B. Kaufman et al. Journal of Electrochemical society, V. 138, 1991). In this subtractive use of protective oxides, evaluation of the oxide film strain properties is important to minimize defectivity during the slurry polishing action. On an opposite approach, it is plausible to utilize the nanoscale self protective oxides an integrated part of microelectronic device manufacturing to grow oxide films that are self limiting in growth and consequently can be used for nanoscale electronic device manufacturing instead of the commonly used film deposition and removal (through CMP and/or etch processes) to achieve thickness control in conventional microelectronics manufacturing. Furthermore, if achieved, this approach will minimize the challenges in integration of one-dimensional nanostructures with microsystems (E.Alaca, International Materials Reviews, forthcoming, 2009).
In summary, growth of thin films and inherent stress development within the film and film/substrate interface are critical for multiple phases of microelectronics manufacturing. Particularly protective oxides of metal films are foreseen to have wide applications as (i) an interfacial layer to improve the adhesion and/or limit penetration of reactive chemicals of a deposited film and substrate as in the case for chip packaging, (ii) as a subtractive layer to achieve selective material removal as in CMP and (iii) as a nanofilm with inherent self growth limiting capability that could be used for nanoscale electronics manufacturing.
The objective of this proposal is to establish a fundamental understanding on dynamic growth of nano-scale protective oxide thin films as they grow in various environments (based on the specific application) through experimentation and simulation. Control of film growth and properties using oxidizers, surface active agents, salts, etc’ in turn will lead to optimized process conditions with improved defectivity and reliability of the current semiconductor manufacturing. In turn, the proposed study will create a basis for the new generation semiconductor industry that is expected to deal with atomic level devices. Fundamental understanding of the proposed research is expected to be utilized in many other fields such as in biological systems i.e. corrosion within bio-implants, dental implants, pacemakers, artificial joints, (Interface, V.17, No 2, 2008) and applications where the interface and thin film properties affect permeation of hydrogen like fusion –reactors and ferroelectric capacitors (J.S. Cross et al, J. of Appl. Phys. 98, 094107, 2005).